1. Field of the Invention
The present invention relates generally to method and structure for manufacturing a flash memory device. The present invention further relates to the method and structure for manufacturing a flash memory device with enhanced gate coupling ratio (GCR) and thereafter a smaller applied control gate voltage needed in the operation of the flash memory device.
2. Description of the Prior Art
Nonvolatile flash memory devices such as erasable programmable read-only memory (EPROM) or electrically erasable programmable read-only memory (EEPROM) or flash memory have been widely used and accepted as data storage devices due to their capabilities to store data after the power is turned off.
Generally, a flash memory device is very similar to a metal oxide semiconductor field effect transistor (MOSFET) except that it has a stacked gate structure. Two gates are provided generally in a stacked manner in a flash memory device, one of which is a floating gate, normally formed by polysilicon for the storage of electrical charges, and the other of which is the control gate to control the access of information. The floating gate is generally located underneath the control gate with a dielectric layer (for example, oxide/nitride/oxide stacked structure) lying between the two gates. The floating gate is named because it is always in the “floating” state without a connection to the exterior circuitry. Instead, the control gate is usually connected to a word line. A gate oxide (sometimes called tunnel oxide) lies between the floating gate and the semiconductor substrate. Additionally, source and drain regions are arranged on the semiconductor substrate on both sides of the gates.
The operation of a flash memory device will be described briefly as follows. During a write operation, a high programming voltage is applied on the control gate, and this forces an inversion region to form in the p-type substrate. The drain voltage is increased to half of the control gate voltage while the source is grounded, and this increases the voltage drop between the drain and the source. In the presence of the inversion region, the current between the drain and the source increases. The resulting high electron flow from the source to the drain increases the kinetic energy of the electrons. This causes electrons to gain enough energy to overcome the silicon/silicon oxide energy barrier and be collected in the floating gate. The floating gate can be erased by grounding the control gate and raising the source voltage to a sufficiently high positive voltage to transfer electrons out of the floating gate to the source gate by tunneling through the thin gate oxide layer.
It is the general trend in the semiconductor market to manufacture devices with miniaturized dimensions, lower operation voltage, lower cost, higher speed, etc. One of the key features of a flash memory device is the gate coupling ratio (GCR) between the floating gate and the control gate, which affects both the operating voltage and device speed. The read/write method of a flash memory is effected by means of electrons transferring between the floating gate and the source/drain gate.
The gate coupling ratio is defined as the ratio of an induced voltage on the floating gate to the incident voltage applied on the control gate. For the perfect coupling, this ratio is equal to 100%. Generally, increasing the gate coupling ratio can lower the operating voltage and increase the device speed at the same time. A few approaches, which have been taken to increase the gate coupling ratio, include: increasing the overlapped area between the floating gate and the control gate; reducing the dielectric thickness between the floating gate and the control gate; and increasing the dielectric constant (k) of the dielectric layer between the floating gate and the control gate.
FIGS. 1A through 1H are schematic cross-sectional views showing the progression of steps for forming a flash memory device according to a prior art. As shown in FIG. 1A, a semiconductor substrate 110 is provided, the semiconductor substrate has a plurality of shallow trench isolation (STI) structures (not shown) therein. A gate oxide layer 111, a first polysilicon (poly 1) layer 112 and a silicon nitride (SiN) layer 113 are sequentially formed over the substrate 110. The poly 1 layer 112 used as floating gate material is usually grown, for example, by chemical vapor deposition. The silicon nitride layer 113, used as an etching mask for the poly 1 layer etching, is usually also grown by chemical vapor deposition.
As shown in FIG. 1B, a photo resist layer 114 is then formed over the top of silicon nitride layer 113 and patterned by a conventional photolithography process. The photo resist layer 114 is used as an etching mask for silicon nitride layer 113 etching.
As shown in FIG. 1C, an etching process is therefore performed on the silicon nitride layer 113. Furthermore, the photo resist is stripped after the etching reaction is completed.
As shown in FIG. 1D, a silicon nitride spacer layer 115 is then deposited onto the surface as well as the side wall of the patterned silicon nitride layer 113. Furthermore, in FIG. 1E, an etching process on the poly 1 layer 112 is performed by using the silicon nitride spacer layer 115 as a self-aligned etching mask. After the self-aligned etching, the silicon nitride layer 113 and the silicon nitride spacer 115 are removed, which is as shown in FIG. 1F.
FIG. 1G shows that an insulating stacked structure 116 is then deposited by using, for example, chemical vapor deposition. The insulating stacked structure is sometimes called inter-poly dielectric because it is used as the dielectric between the floating gate (poly 1) and the control gate (poly 2).
FIG. 1H shows that a second polysilicon (poly 2) layer 117 is then deposited and patterned. The poly 2 layer forms the control gate of the flash memory device. After the poly 2 layer etching, drain and source formation (not shown) is therefore conducted by conventional ion implantation process.
In the prior art, the floating gate surface area is the floating gate periphery length times the floating gate width “Lw”. As shown in FIG. 11, the floating gate is drawn in a three-dimensional illustration in order to clearly show how the floating gate surface area is calculated. The floating gate height 312 is typically of thickness 800 Angstroms (A). The floating gate length 314 is typically 2500 A. The floating gate width 313 herein is designated as “Lw”. Therefore, the floating gate surface area that is effectively coupled to the control gate is the sum of area 311, area 315 and area 316. Therefore,Floating gate surface area (for the prior art)=(800+2500+800)×Lw=4100Lw 
In the prior art as described above, the surface area of the floating gate overlapped with that of the control gate is limited, which results in a gate coupling ratio of only 60%. It would therefore be desirable to provide a manufacturing method for a flash memory device with a larger surface area of the floating gate overlapped with that of the control gate so that a higher gate coupling ratio can be obtained.